The performance of semiconductor device substrates can be modified by exerting mechanical stresses. For example, hole mobility can be enhanced when the channel region is under compressive stress, while the electron mobility can be enhanced when the channel is under tensile stress. Thus, compressive and/or tensile stresses can be provided in the channel regions of a p-channel field effect transistor (pFET) and/or an n-channel field effect transistor (nFET) to enhance the performance of such devices.
Accordingly, stressed silicon channel region may be provided by forming embedded silicon germanium (SiGe) or silicon carbon (Si:C) stressors within the source and drain regions of a complementary metal oxide semiconductor (CMOS) device, which induce compressive or tensile strain in the channel region located between the source region and the drain region.
Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices with thin channels are promising candidates to provide superior device scaling for future technology nodes. However, the use of embedded stressors such as SiGe and Si:C that are used in current CMOS to boost transistor performance is not straightforward with thin-channel devices. For example, integrated embedded stressors with thin channel transistors exhibit drawbacks in terms of increased junction capacitance and leakage.
FIG. 1 shows a related art semiconductor structure 100 of a MOSFET with a thin channel region 110 located between a BOX layer 120 and a dielectric layer 130. To ensure that the electrostatic integrity of the device is not degraded, the embedded stressor 140 has to be either undoped or lightly doped at the bottom to allow heavier doping above the BOX. Some well doping is still required in the region below the BOX layer to prevent a possible punch-through. Also, to ensure that there is enough doped material for contact formation raised source/drain (S/D) regions are provided, which, however, leads to higher parasitic capacitance.